The present invention relates to the field of data transmission between fast memory components, and between the memory components and a memory control unit and, more particularly, the field of generating synchronous control signals for a parallel/serial converter that converts parallel send data in a memory interface circuit to a serial send data stream.
The transmission of data between semiconductor memory components of the existing generation proceeds at a relatively low transmission rate using a bidirectional low-speed bus with separated ports for data, addresses and commands, and send interface circuits performing a serial data transmission at the very high transmission rates of future memory generations do not currently exist.
The future memory generations, for example, of DDR-DRAM memories, will have very high transmission frequencies and be subject to a variety of limitations: the send interface circuit of future semiconductor memories of this type is to have, on the one hand, low power consumption and, on the other hand, transmit the data at the required high transmission frequencies so that there exists a tradeoff between high transmission frequencies, that is, higher power consumption and the need to reduce power consumption to avoid overheating or increase battery life time in mobile applications.
For this purpose, a signal generator for synchronous generation of the clock and control signals employed in the send interface circuits of future semiconductor memory generations is required that is equipped to adjust the temporal position of these clock and control signals to the individual system requirements and optionally shall be able to switch off the send interface during times when there is no data sending required.